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| WS74HC164 GENERAL DESCRIPTION 8-Bit Serial-in/Parallel-out Shift Register 74HC164 is fabricated in the high-speed silicon gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices (LS-TTL). This 8-bit Shift Register has AND-gated serial inputs and clear. Each register bit is a D-type master-slave flip-flop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables another input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only data meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive edge of the clock pulse. Clear is independent of the clock and accomplished by a low level at the clear (CL) input. 74HC164 logic is functionally as well as pin-out compatible with the standard LS164. All inputs are protected from ESD damage by internal diode clamps to Vcc and ground. FEATURES * Wide operating supply voltage range: 2-6V. * Asynchronous master reset CL active at low * Date serially shifted at the positive edge of clock CK A B Q1 Q2 Q3 Q4 GND 1 14 VCC Q8 Q7 WS74HC164 * Low input current: < 1A. * Low quiescent supply current: 80A maximum * Output driving capability: standard Q6 Q5 CL LOGIC DIAGRAM 7 8 CK 8 CK SERIAL INPUTS A B 1 2 CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK D CK D CL Q D CL Q D CL Q D CL Q D CL Q D CL Q D CL Q Q CL 9 CL Q1 3 Q2 4 Q3 5 Q4 6 Q5 10 Q6 11 Q7 12 Q8 13 FUNCTIONAL DESCRIPTION 1. Truth Table Inputs Outputs CL L H H H H CK X L A X X H L X B X X H X L Q1 L Q1O H L L Q2 L ... Q2O Q1N Q1N Q1N Q8 L Q8O Q7N Q7N Q7N H = High Level (steady state). L= Low Level (steady state) X = don't care (any input, including transitions) = Transition from low to high level. Q1O , Q2O , Q8O = the level of Q1 , Q2 , Q8 , respectively, before the indicated steady state input conditions were established. Q1N , Q7N = The level of Q1 or Q7 before the most recent transition of the clock; indicates a one-bit shift. 1 WS74HC164 2. Logic Waveform CL SERIAL INPUTS A B CK Q1 Q2 Q3 Q4 OUTPUTS Q5 Q6 Q7 Q8 CLEAR CLEAR ABSOLUTE MAXIMUM RATINGS Parameter Value Unit DC supply voltage (Vcc) - 0.5 ~ + 7.0 V DC input or output Voltage (VIN, VOUT) -0.5 to Vcc +0.5 V DC Current Drain per pin, any output (Iout) 25 mA DC Current Vcc or GND (Icc) 50 mA Storage Temperature( TSTG) -65 ~ +150 Power Dissipation (PD ) 500 mW Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. RECOMMENDED OPERATING CONDITIONS Parameter DC Supply Voltage (Vcc) Min. 2 Typ. 5 Max. 6 Unit V Input / output Voltage (VIN, VOUT) 0 Vcc V Vcc = 2 V 1.5 VIH High-level Input Voltage Vcc = 4.5 V 3.15 V Vcc = 6 V 4.2 Vcc = 2 V 0.5 VIL Low-level Input Voltage Vcc = 4.5 V Vcc = 6 V 1.35 1.8 V Input Rise/Fall Times (tr/tf Vcc = 2 V Vcc = 4.5 V Vcc = 6 V 1000 500 400 ns Operating Temperature (TA) 74HC164 -40 +85 Note 2: All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. 2 WS74HC164 DC ELECTRICAL CHARACTERISTICS ( apply across temperature range unless otherwise specified) TA25 C Min. Typ. Max. o TA=-40~85 Parameter Test Conditions Vcc Min. Max. Unit 2V 1.9 1.998 1.9 IOH = -20uA 4.5V 4.4 4.499 4.4 VOH VI=VIH or VIL IOH = -4mA 6V 5.9 5.999 5.9 V 4.5V 3.98 4.3 3.84 IOH = -5.2mA 6V 5.48 5.8 5.34 2V 0.002 0.1 0.1 IOH = 20uA 4.5V 0.001 0.1 0.1 VOL VI=VIH or VIL IOH = 4mA 6V 0.001 0.1 0.1 V 4.5V 0.17 0.26 0.33 IOH = 5.2mA 6V 0.15 0.26 0.33 II VI = VCC or 0 6V 0.1 100 1000 nA ICC VI = VCC or 0, IO = 0 6V 8 80 A Ci 2V6V 3 10 10 pF TIMING REQUIREMENTS OVER RECOMMENDED OPERATING TEMPERATURE RANGE (unless otherwise noted) Parameter Vcc TA25 C Min. Max. o TA=-40~85 Min. Max. Unit fclock Clock frequency 2V 4.5V 6 31 5 25 MHz 6V 36 28 2V 100 125 CL low tw Pulse duration CK High or low 4.5V 20 25 6V 17 21 ns 2V 4.5V 6V 80 16 14 100 20 18 2V Data ts Setup time before CK 100 20 125 25 4.5V 6V 17 21 ns 2V CL inactive 100 20 17 5 125 25 21 5 4.5V 6V 2V th Hold time Data after CK 4.5V 6V 5 5 5 5 ns 3 WS74HC164 AC ELECTRICAL CHARACTERISTICS (CL=50pF) Parameter From Input To Output Vcc TA25 C Min. Typ. Max. o TA=-40~85 Max. Unit Min. 2V 6 10 5 fmax 4.5V 31 54 25 MHz 6V 36 62 28 2V 140 205 255 tPHL CL Any Q 4.5V 28 41 51 ns 6V 24 35 46 2V 115 175 220 tpd CK Any Q 4.5V 23 35 44 ns 6V 20 30 38 2V 38 75 95 tt 4.5V 8 15 19 ns 6V 6 13 16 Parameter Cpd Power Dissipation Capacitance Test Conductions o TA=25 C, NO LOAD Typ. 135 2 * fi + Unit pF Note 3 : CPD determines the no load dynamic power consumption , PD=CPD* Vcc load dynamic current consumption, Is = CPD * Vcc* fi + Icc. Icc * Vcc, and the no AC SWITCHING WAVEFORM AND AC TEST CIRCUIT 1/f MAX ts (DATA) CLOCK 50% 90% 50% 10% tf 50% 10% 90% VCC GND tr VCC tw (CK) DATA 50% th 50% GND VCC tw (CL) CLEAR 50% 50% GND ts (CL) tPLH tPHL VOH Q 50% tPHL 50% 50% VOL AC Switching Waveform 4 WS74HC164 Q1 A Q2 Q3 Q4 Q5 CL Q6 Q7 Q8 INPUTS B CK CL AC Testing Circuit PIN DESCRIPTION PIN NO. SYMBOL DESCRIPTION 1, 2 3, 4, 5, 6, 10, 11, 12, 13 7 8 9 14 A, B Q1 - Q8 GND CK CL VCC Data Inputs Outputs Ground (0V) Clock input (active at rising edge) Master reset input (active at Low) Positive power supply A B 1 14 VCC Q8 Q7 Q6 Q5 1 2 A B Q1 Q2 Q3 Q4 3 4 5 6 10 11 12 13 Q1 Q2 Q3 Q4 Q5 8 9 CK Q6 Q7 Q8 CL 7 8 CK CL GND Pin Configuration (DIP14) Logic Symbol PAD DIAGRAM Q7 Q8 Q6 Q5 CL The Coordinate of Each Pad Q1 (-395.1, -452.8) Q2 (-138.3, -452.8) Q3 ( 149.9, -452.8) Q4 (355.4, -308.2) GND (355.4, - 82.2) CK (338.7, 61.8) Q5 (305.0, 362.8) Q6 ( 48.2, 362.8) Q7 (-240.0, 362.8) Q8 (-445.5, 214.6) Vcc (-445.5, - 3.8) A (-428.8, -148.8) B (-430.7, -288.8) HC164 Vcc A B Q1 Q2 Q3 Die Size = 46 mil x 49 mil Pad size = 90 um x 90 um CK GND Q4 CL (340.6, 201.8) Note 4: Substrate should be connected to Vcc or left it open. 5 |
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